@erwang 我们的书已经出版了，《视频编解码芯片设计原理》https://item.jd.com/10059208033891.html

Introduction

xkISP is an open source image signal processor (ISP) based on Xilinx HLS development tools. xkISP is jointly developed by VIP Lab of Fudan university and DAMO CTL lab of Alibaba. Up to now, xkISP supports to process 12-bit raw image data of any resolution. The entire pipeline includes 17 function modules shown in the following:

File Structure

xkISP
├─fpga
│      host.cpp
│      top.cpp
│      top.h
│      xcl2.cpp
│      xcl2.h
│     
├─src
│    isp_top.h
│    file_define.h
│    "*module*".cpp
│    "*module*".h
│    ...
│   
├─tb
│     tb_"*module*".cpp
│    ...
│   
├─tcl
│      Makefile
│      "*module*".tcl
│      "*module*"_directives.tcl
│    ...
│   
├─tv
│     Makefile
│     hls_param.txt
│     input.raw
│     isp
│     readme_for_tv
├─  LICENSE
├─  setup_env.sh
└─  README.md

• fpga contains code files for top level integration verification.
• src contains source code files which are the single module of the xkISP project and head files(file_define.h) for single module test.
• tb contains code files for verificating the function consistency with Cmodel(tv/isp) in the module level.
• tcl contains the scripts for execuating the code files in the tb("module".tcl) and adding the pragma command for the code files in the src ("module"_directives.tcl). Makefile in the tcl is used for module level verification.
• tv contains the files for generating the test vectors. You can read the readme_for_tv for more details. setup_env.sh is used to designate the development tools. (Vitis HLS or Vivado)

Download

Clone this repo in Github:

git clone https://github.com/openasic-org/xkISP.git
cd xkISP

目前我们开源版本没有解码器，企业合作版本是有解码器的

https://github.com/openasic-org/xkISP

@vvrobinham 好的 我稍后加你

@fly1198721171 你好！根据我们前期开发下来的经验，我们目前暂时不接受外部开发者，主要考虑到硬件开发过程中的流程比较复杂，外部开发者难以持续时间投入

0_1629349150915_H264 ENCODER RTL V2.0仿真及FPGA教程_v2.pptx

Descripton

A tiny software to translate bit-stream from RTL (ASCII text) to h264 bit-stream (binary)

input ASCII text format

/test/bs_416x240_g5_f10_q27.dat (exmaple)
@0 -- frame number 0, added manually
XX -- bit stream byte generated by RTL testbench
XX
XX
....
@1
XX
XX
XX
....

output bitstream

/test/bs.264

run

/test/bs2h264.exe

download

0_1629349087470_bs2h264_v1.0.zip

http://openasic.org/topic/45/bs2hevc?_=1605587114608&loggedin=true
请看这个软件

IP SoC China 2020
网址：https://www.design-reuse-embedded.com/ipsocdays/ipsocdays2020/china2020/welcome.jsp

视频地址：
https://www.design-reuse-embedded.com/ipsocdays/ipsocdays2020/china2020/video.jsp?k=Yibo%2BFan

优酷地址：
https://v.youku.com/v_show/id_XNDg0NzA1MzE1Mg==.html?spm=a1z3jc.11711052.0.0&isextonly=1