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    Posts made by bo

    • RE: 请问会提供xkISP在FPGA上运行的demo吗?

      目前可以用U200/U250这种大容量FPGA运行的,带摄像头的FPGA目前还没找到合适的支持RAW数据输入的摄像头模块

      posted in xkISP
      B
      bo
    • RE: H.265V2.0性能和使用问题

      是的 可以用在国产FPGA上,开源代码使用没有限制,是免费的

      posted in 交流讨论 | General Discussion
      B
      bo
    • RE: 企业商务合作没有在主页上看到具体链接,请问是否有开通这个功能的计划?

      @林炸虾 欢迎联系 bo@xksilicon.com

      posted in 问题反馈 | Comments & Feedback
      B
      bo
    • RE: 关于这个开源项目 from VIP Lab

      @erwang 我们的书已经出版了,《视频编解码芯片设计原理》https://item.jd.com/10059208033891.html

      posted in 新闻文档 | News & Documents
      B
      bo
    • xkISP - Open Source ISP IP Core

      Introduction

      xkISP is an open source image signal processor (ISP) based on Xilinx HLS development tools. xkISP is jointly developed by VIP Lab of Fudan university and DAMO CTL lab of Alibaba. Up to now, xkISP supports to process 12-bit raw image data of any resolution. The entire pipeline includes 17 function modules shown in the following:

      alt text

      File Structure

      xkISP
      ├─fpga
      │      host.cpp
      │      top.cpp
      │      top.h
      │      xcl2.cpp
      │      xcl2.h
      │     
      ├─src
      │    isp_top.h
      │    file_define.h
      │    "*module*".cpp
      │    "*module*".h
      │    ...
      │   
      ├─tb
      │     tb_"*module*".cpp
      │    ...
      │   
      ├─tcl
      │      Makefile
      │      "*module*".tcl
      │      "*module*"_directives.tcl
      │    ...
      │   
      ├─tv
      │     Makefile
      │     hls_param.txt
      │     input.raw
      │     isp
      │     readme_for_tv
      ├─  LICENSE
      ├─  setup_env.sh
      └─  README.md
      
      • fpga contains code files for top level integration verification.
      • src contains source code files which are the single module of the xkISP project and head files(file_define.h) for single module test.
      • tb contains code files for verificating the function consistency with Cmodel(tv/isp) in the module level.
      • tcl contains the scripts for execuating the code files in the tb("module".tcl) and adding the pragma command for the code files in the src ("module"_directives.tcl). Makefile in the tcl is used for module level verification.
      • tv contains the files for generating the test vectors. You can read the readme_for_tv for more details. setup_env.sh is used to designate the development tools. (Vitis HLS or Vivado)

      Download

      Clone this repo in Github:

      git clone https://github.com/openasic-org/xkISP.git
      cd xkISP
      
      posted in 代码发布 | OpenASIC Code Release
      B
      bo
    • RE: 请问是否有开发H.265解码器的计划

      目前我们开源版本没有解码器,企业合作版本是有解码器的

      posted in 交流讨论 | General Discussion
      B
      bo
    • xkISP@Github

      https://github.com/openasic-org/xkISP

      posted in xkISP
      B
      bo
    • RE: 对于想参加项目开发的同学

      @vvrobinham 好的 我稍后加你

      posted in 交流讨论 | General Discussion
      B
      bo
    • RE: 对于想参加项目开发的同学

      @fly1198721171 你好!根据我们前期开发下来的经验,我们目前暂时不接受外部开发者,主要考虑到硬件开发过程中的流程比较复杂,外部开发者难以持续时间投入

      posted in 交流讨论 | General Discussion
      B
      bo
    • H264 ENCODER RTL V2.0仿真及FPGA教程_v2

      0_1629349150915_H264 ENCODER RTL V2.0仿真及FPGA教程_v2.pptx

      posted in 新闻文档 | News & Documents
      B
      bo
    • Bs2H264 SW Code

      Descripton

      A tiny software to translate bit-stream from RTL (ASCII text) to h264 bit-stream (binary)

      input ASCII text format

      /test/bs_416x240_g5_f10_q27.dat (exmaple)
      @0 -- frame number 0, added manually
      XX -- bit stream byte generated by RTL testbench
      XX
      XX
      ....
      @1
      XX
      XX
      XX
      ....

      output bitstream

      /test/bs.264

      run

      /test/bs2h264.exe

      download

      0_1629349087470_bs2h264_v1.0.zip

      posted in 代码发布 | OpenASIC Code Release
      B
      bo
    • RE: H265 2.0的RDO流程

      http://openasic.org/topic/45/bs2hevc?_=1605587114608&loggedin=true
      请看这个软件

      posted in 交流讨论 | General Discussion
      B
      bo
    • IP SoC China 2020 演讲Video

      IP SoC China 2020
      网址:https://www.design-reuse-embedded.com/ipsocdays/ipsocdays2020/china2020/welcome.jsp

      视频地址:
      https://www.design-reuse-embedded.com/ipsocdays/ipsocdays2020/china2020/video.jsp?k=Yibo%2BFan

      优酷地址:
      https://v.youku.com/v_show/id_XNDg0NzA1MzE1Mg==.html?spm=a1z3jc.11711052.0.0&isextonly=1

      posted in 新闻文档 | News & Documents
      B
      bo
    • RE: H265 2.0的RDO流程

      @lunning 3.0目前还在内部开发,开源时间未定。

      posted in 交流讨论 | General Discussion
      B
      bo
    • RE: http://soc.fudan.edu.cn/vip网址等不上去

      @cao 网址改了: http://viplab.fudan.edu.cn

      posted in 问题反馈 | Comments & Feedback
      B
      bo
    • RE: H265 2.0的RDO流程

      这一版本没有实现RDO功能。
      RDO在我们内部规划的3.0版本中有的

      posted in 交流讨论 | General Discussion
      B
      bo
    • RE: H265顶层接口变量代表的意思

      这个我们未来会整理一个更详细的使用说明文档。
      目前你可以参考testbench的接口设计方法来做

      posted in 交流讨论 | General Discussion
      B
      bo
    • RE: 开源H.265/HEVC Encoder IP Core V2.0发布

      未来我们会推出开源版的FPGA实例,可以包括AXI总线接口、软件驱动程序,简单的Demo等

      posted in 新闻文档 | News & Documents
      B
      bo
    • RE: 开源H.265/HEVC Encoder IP Core V2.0发布

      @Giljohn 这个代码不包括编码器外围电路(总线接口,地址管理,Buffer缓存等),enc_top仅仅是编码器核心IP的顶层。如果需要在FPGA上运行,需要自行封装AXI总线接口。

      posted in 新闻文档 | News & Documents
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      bo
    • OpenASIC @GitHub Release

      https://github.com/openasic-org

      Any code update can be found in our Github project

      posted in 代码发布 | OpenASIC Code Release
      B
      bo