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intra prediction我们分成两个部分，pre intra做mode decision，post intra 做partiton decision。 目前版本的代码mode decision只传一个mode给post intra。 后期要预测的更准的话，需要多传几个mode。目前我们自己实验室测试下来，传8个mode给post intra就预测的很准了。

请教一下真正高效的fpga设计和视频芯片设计方法

@wangjiangtao ? 啥意思

这个是mode decision. 后面写在另外一个模块里了，没放在md模块里面

关于硬件开源，真的是太难得了。这些代码不止有研究学习的价值，善于利用，也有巨大的商业价值。范老师真的让人能感受到一个学者的风采。真的希望范老师的开源项目能够真正成为产学研合作的样板。希望一些有社会责任的企业，可以和实验室形成真正的合作。

Update to bs2hevc_v1.1 add command line options. type "-help" for more information

@eesiukei 目前还没有。

@shen_lee x_total y_total 超过你要的边界， 还需要padding出边界到64的倍数

@Scofield 我们正在做这方面的工作

@ruibo 这个不是我们开发的代码，我也搞不清楚，你可以问问原作者

请问，demo的内核没有正常启动，是uboot没有设置正确么？

直接使用开源版本 无需License

@nicu_233 同样的问题 请问前辈解决了吗

H265ENC V2.0 Feature Improvement h265enc v2.0 a. Update the I/P prediction algorithms, and the hardware pipeline to improve the coding efficiency b. Fix the bugs in the previous version c. Check the RTL V2.0 by nLint, and fix the errors and warnings d. Meet the 400MHz synthesized by Design Complier，and fix critical path，warning e. IP Core V2.0 has been validated by the FPGA PreI – Intra mode decision a. Support CTU-level Rate control，based on the CABAC bit number to change the QP adaptively PosI – Intra partition decision a. Prediction for the partition decision is based on the original pixels b. The RD cost for the partition decision is based on the SATD and simplified rate estimation IME – Integer motion estimation a. Configurable IME parameters by the ime_cfg.dat, such as the search range, search center , and search shape b. Extend the search range to ±64 c. By the H-V SRAMs, the search direction of novel IME can be the slope d. By the Bit Truncation, the pixels bit depth is truncated into 4 bit from 8bit with only less than 1dB PSNR loss, but with great improvement on the area and power FME – Fractional motion estimation a. Support the SKIP and MERGE decision by the RD cost similar to the FME decision b. Fix the bugs in the interpolation REC – Reconstruction loop a． Support Intra CTU in Inter Frame by the costs from PosI and FME to decide I/P of current CTU b． Support the SKIP CU, where the prediction samples will be the reconstruction samples c． Rearrange the DCT RTL and fix the bugs DBSAO – Deblocking filter & sample adaptive offset a. Update the DB filter order and remove the transpose memory to reduce memory usage b. Support the SAO EO mode CABAC – Entropy coding a. Update the RTL and fix the bugs b. Support SKIP、MERGE、Intra CTU in Inter Frame and so on c. Remove the ROM in the previous version

请问这个Xilinx FPGA是哪一个系列的呢 打扰了 期待您的回复

@wjl3258 看如下网址： https://blog.csdn.net/yangyuf012/article/details/81277027?ops_request_misc=&request_id=&biz_id=102&utm_source=distribute.pc_search_result.none-task-blog-SOBAIDUWEB-0

我看视频输入格式只支持YV12，即planar格式，你看看你的输入是不是semi-planar的。