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    db mv更新疑问。

    Scheduled Pinned Locked Moved xkHEVC IP Core
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    • H Offline
      huvas
      last edited by huvas

      范老师您好:
      感谢范老师开源265 、264代码,在阅读代码中我受益很多。
      同时有一个疑问:如下代码中left_mv在第一列LCU中没有被取值。那么在第二列LCU中
      mv_pre_up_r <= left_mv[cnt_r[7:5]-3'd1] ;
      mv_pre_dn_r <= left_mv[cnt_r[7:5]] ;
      这里拿到的left_mv是否为无效值。

      //*** store left mv ***************************************
          assign mv_data_o_w = ((cnt_r[8:5] == 0) && (cnt_r[1:0] == 0)) ? top_mv_data_o_w : cur_mv_data_o_w ;
          always @ ( posedge clk or negedge rst_n ) begin 
              if ( !rst_n ) begin
                  left_mv[0]      <= 0      ;
                  left_mv[1]      <= 0      ;
                  left_mv[2]      <= 0      ;
                  left_mv[3]      <= 0      ;
                  left_mv[4]      <= 0      ;
                  left_mv[5]      <= 0      ;
                  left_mv[6]      <= 0      ;
                  left_mv[7]      <= 0      ;
              end else if ( sys_ctu_x_i == 0 ) begin //第一列LCU不更新
                  left_mv[0]      <= 0      ;
                  left_mv[1]      <= 0      ;
                  left_mv[2]      <= 0      ;
                  left_mv[3]      <= 0      ;
                  left_mv[4]      <= 0      ;
                  left_mv[5]      <= 0      ;
                  left_mv[6]      <= 0      ;
                  left_mv[7]      <= 0      ;
              end else if (cnt_r[8:5]>0 && cnt_r[4:2] == 3'b111) begin 
                  left_mv[cnt_r[8:5]-3'd1] <= cnt_r[1:0] == 2'd0 ? mv_data_o_w : left_mv[cnt_r[8:5]-3'd1] ;
              end 
          end 
        always @ ( posedge clk or negedge rst_n ) begin 
              if ( !rst_n )begin 
                  mv_pre_up_r  <= 0;
                  mv_pre_dn_r  <= 0;
              end 
              else if (cnt_i == 0) begin                     
                  mv_pre_up_r  <= tl_mv ;                   
                  mv_pre_dn_r  <= left_mv[0] ;            
              end else if (cnt_i[4:2] == 0) begin             
                  mv_pre_up_r  <= left_mv[cnt_r[7:5]-3'd1] ;  
                  mv_pre_dn_r  <= left_mv[cnt_r[7:5]] ;
              end else if (cnt_r[1:0] == 2'b11) begin         
                  mv_pre_up_r  <= mv_cur_up_r;
                  mv_pre_dn_r  <= mv_cur_dn_r;
              end 
              else begin 
                  mv_pre_up_r  <= mv_pre_up_r;
                  mv_pre_dn_r  <= mv_pre_dn_r;
              end 
          end 
      
      
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