是的，需要更新的， 我做过decoder，就是这么做的

Video Demo

Links
video demo 中文
video demo English ,sorry about poor english.

@bo
可能是文件格式不对7z上传了不能显示，zip和pdf可以

RTL Code, TestBench,C Model and tiny softwares

Download
OSenLogic264decoder.zip

@bo demo video 1080p
http://pan.baidu.com/s/1hswwUES

@bo 范老师你好， 论坛的附件上传显示100%, 但是好像不能下载， 我先传到网盘吧，里面有C Model， RTL Code， modelsim 写入二进制文件的源码及dll文件， ascii转binary的软件。下载地址发站内信给你了。

Brief
Model Osen Logic OSD10 h.264 decoder
Profile Baseline
Level 3.1
Input Format H.264 NAL stream
Output Format YUV4:2:0
Bitdepth 8
Slice type supported I,SI,P,SP
Entropy Coding CAVLC
Supported frme size Max: 1920x1088,Min:640x480
Supported bitrate 0 to 10Mps,No decode rate control
Max resolution and frame rate 1920x1088 @ 30fps, working at 75M
Required external memory size 32Mbyte
Memory interface data width 64bit

Doc Download:
Osenlogic_OSD10_datasheet.pdf

我也提供baseline的c model，解码后的yuv和JM86或ffmepg对比是bit-to-bit正确的。我的testbench也生成yuv.txt，用hex2bin转为yuv二进制文件后， 可以和软件模型对比， 也是bit to bit对应的。

大学和毕业后我做了一个h.264 decoder， 现在已应用在无人机的工程里，现在我想公开一个不带deblock的版本在这里, deblock版本不开源， deblock一个宏块只需50多个时钟，和其他过程可以同步进行，所以基本不影响解码速度。
General Description
Features
The Osen Loigc OSD10 core is a hardware implementation of the H.264
baseline video compression algorithm.
It is Simple, fully synchronous design with low operating freqency.
Supports up to the highest HDTV video resolution (1920x1080 @
30 fps progressive) on FPGA.
Simple, fully synchronous design.
Single core HDTV support in FPGA : 720p (1280x720) at 60 fps or
1080p(1920x1080) at 30fps in High end FPGAs (Zynq7020 lowest speed grade).
Fast Deblocking Filter:Only 60 Clocks are needed to deblock a 16x16 block.
No CPU required for decoding.
Very low latency decoding
Any Motion vector is supported.
Support for all of intra4x4 and all intra16x16 modes except IPCM.
Multiple slices supported.
Deblocking filter for better quality.
External memory interface tolerant of high latencies and delays,
ideal in a SoC system or in a shared bus with a CPU. The memory
interface can be clocked at a different frequency from the core for
easier integration.
Supports YUV 4:2:0 video output.
Min Clock speed = about 1.4 x the raw pixel clock speed.
Very low operational frequency : from 15 MHz for VGA @ 30
fps to ~75 MHz for 1920x1080 @ 30 fps.
Available as synthesizable Verilog Netlist.

说明如下：
[0_1496925861235_Osenlogic_OSD10_datasheet.docx](Uploading 100%)