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    首款开源H.265 Video Encoder IP Core发布

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    • B Offline
      bo
      last edited by bo

      H.265 Video Encoder IP Core

      开源H.265 硬件视频编码器

      H.265 Video Encoder IP Core 是开源的H.265硬件视频编码器，实现了H.265（或叫HEVC）的大部分功能。它由复旦大学专用集成电路与系统国家重点实验室（State Key Lab of ASIC & System，Fudan University）视频图像处理器实验室（VIP Lab）范益波教授研究团队开发完成，并开放源代码。任何组织个人可以无偿使用上述代码用于研究和生产目的，VIP Lab将会持续更新并维护H.265硬件视频编码器的开发。

      基本Feature

      • HEVC/H.265 Main Profile
      • YUV 4:2:0
      • Bitdepth 8
      • 4K@30fps, 400MHz
      • GOP: I/P
      • CU: 8x8~64x64
      • PU: 4x4~64x64
      • TU: 4x4/8x8/16x16/32x32
      • 1/4 Sub-pixel
      • Search range 32
      • All 35 Intra prediction mode
      • CABAC
      • Deblocking Filter
      • SAO
      • Rate control: CBR/VBR (Software)

      关于VIP Lab

      复旦大学VIP实验室专注于从事下一代视频、图像硬件处器研究，包括超高清视频编码器（H.264/H.265 Video Encoder IP），图像去雾（Dehazing）处理器，双目视觉处理器（Stereo Matching）等。
      实验室网站 http://viplab.fudan.edu.cn

      代码下载

      http://www.openasic.org/topic/6/h265-video-encoder-rtl-ip-core-version-1-0

      关注我们

      微信公众号： OpenASIC
      img

      1 Reply Last reply Reply Quote 2
      • B Offline
        brucezhan
        last edited by

        ----4K@30fps, 400MHz
        FPGA?ASIC? What's the process?

        B 1 Reply Last reply Reply Quote 0
        • Y Offline
          yoyolxzhang
          last edited by

          谢谢分享，正在学习中

          1 Reply Last reply Reply Quote 0
          • T Offline
            Timmy
            last edited by

            请问这个IP的硬件资源消耗是什么情况呢，能不能分享具体数据？

            B 1 Reply Last reply Reply Quote 0
            • B Offline
              bo @Timmy
              last edited by

              @Timmy 最简单的方法是自己跑个dc综合，或者FPGA综合。

              1 Reply Last reply Reply Quote 0
              • Z Offline
                zhuzhuqing0
                last edited by

                @范老师，能否提供和RTL匹配的C或C++作为研究（而且仿真的时候是要和golden数据对比的），谢谢~

                B 1 Reply Last reply Reply Quote 0
                • M Offline
                  maurice
                  last edited by

                  Is this IP based on SW? or pure HW?
                  How about the max compressing rate is? and the lowest latency?

                  B 1 Reply Last reply Reply Quote -1
                  • Y Offline
                    yx9527
                    last edited by

                    老师，晒个psnr曲线呗

                    B 1 Reply Last reply Reply Quote 0
                    • B Offline
                      bo @brucezhan
                      last edited by

                      @brucezhan Not FPGA, If you use 65nm, it can reach 400MHz

                      1 Reply Last reply Reply Quote 0
                      • B Offline
                        bo @zhuzhuqing0
                        last edited by

                        @zhuzhuqing0 C Model 后期我会出个软件给大家，方便大家使用。

                        F 1 Reply Last reply Reply Quote 0
                        • B Offline
                          bo @maurice
                          last edited by

                          @maurice Pure HW， written by Verilog HDL (RTL)

                          1 Reply Last reply Reply Quote 0
                          • B Offline
                            bo @yx9527
                            last edited by

                            @yx9527 后面出个参考软件给大家，自己跑吧 😃
                            说实话，目前曲线上结果不是太好，别期望太高哦。正在进一步改进中

                            1 Reply Last reply Reply Quote 0
                            • F Offline
                              fighting @bo
                              last edited by

                              @bo 范老师，C Model大概什么时候发布？会发布源代码吗？

                              B 1 Reply Last reply Reply Quote 0
                              • B Offline
                                bo @fighting
                                last edited by

                                @fighting C Model暂时不开放源代码，会对参与项目开发的人员开放代码。一般用户其实只需要RTL就够了

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                                • K Offline
                                  kelly
                                  last edited by

                                  范老师，您好！ 我一部分工作是作视频处理算法的，从事IC设计有十余载，希望有机会可以参与贵团队的工作，无论编码、设计、架构、优化都可以。 真的非常高兴国内有越来越多这样的共创平台。

                                  B L 2 Replies Last reply Reply Quote 0
                                  • K Offline
                                    kelly
                                    last edited by

                                    我用synopsys － DVE （or say VCS） 将仿真跑起来了，目前run 正常无报错

                                    Chronologic VCS simulator copyright 1991-2014
                                    Contains Synopsys proprietary information.
                                    Compiler version I-2014.03-2_Full64; Runtime version I-2014.03-2_Full64; Dec 26 15:02 2016
                                    ucli% run

                                    *** CHECK TOP ! ***

                                                 fime auto check is on
             fme auto check is on
             mvd auto check is on
             db auto check is on
             fetch auto check is on
             bs auto check is on

                                    *** TEST P FRAMES ! ***

                                        at 00000600, Frame Number = 00, mb_x_first = 00, mb_y_first = 00
    at 00050065, Frame Number = 00, mb_x_first = 01, mb_y_first = 00
    at 00091015, Frame Number = 00, mb_x_first = 02, mb_y_first = 00
    at 00131965, Frame Number = 00, mb_x_first = 03, mb_y_first = 00
    at 00172915, Frame Number = 00, mb_x_first = 04, mb_y_first = 00
    at 00213865, Frame Number = 00, mb_x_first = 05, mb_y_first = 00
    at 00273695, Frame Number = 00, mb_x_first = 06, mb_y_first = 00
    at 00314645, Frame Number = 00, mb_x_first = 00, mb_y_first = 01
    at 00355595, Frame Number = 00, mb_x_first = 01, mb_y_first = 01
    at 00396545, Frame Number = 00, mb_x_first = 02, mb_y_first = 01
    at 00437495, Frame Number = 00, mb_x_first = 03, mb_y_first = 01
    at 00478445, Frame Number = 00, mb_x_first = 04, mb_y_first = 01
    at 00519395, Frame Number = 00, mb_x_first = 05, mb_y_first = 01
                                    1 Reply Last reply Reply Quote 0
                                    • B Offline
                                      bo @kelly
                                      last edited by

                                      @kelly 赞！

                                      1 Reply Last reply Reply Quote 0
                                      • K Offline
                                        kelly
                                        last edited by

                                        范老师, 如果真想拿个asic SoC 项目把这个VENC 集成进去
                                        －－这其实也是件很快的事情，因为我本来就有这样的SoC项目，用的是verisillicon的h.265；
                                        跑一跑SoC的top仿真，
                                        以及放到emulator上也就是用FPGA搭建的emulation的环境上跑跑的话，
                                        还是需要更多测试例的，如果能开放相应的C model就好了，
                                        我可以将C model 修改得更接近UVM平台 得架构， 对关键模块及节点进行自动化实时数据对比。
                                        我真的非常急切渴望知道和确定RTL代码的实际可用性！

                                        1 Reply Last reply Reply Quote 0
                                        • K Offline
                                          kelly
                                          last edited by

                                          或者，范老师，不知道是否方便联系您？

                                          B 1 Reply Last reply Reply Quote 0
                                          • B Offline
                                            bo @kelly
                                            last edited by

                                            @kelly 请联系我吧。 我email: fanyibo@fudan.edu.cn

                                            1 Reply Last reply Reply Quote 0
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