<![CDATA[新闻文档 | News & Documents]]>http://www.openasic.org/category/3RSS for NodeFri, 07 Aug 2026 16:22:10 GMTWed, 21 Jun 2023 04:22:23 GMT60<![CDATA[xkAVC Encoder (K3.pe) Evaluation Edition Released]]>

  • Download
    http://xk.openasic.org/product/3

  • Q&A
    Any question can be submit here : http://openasic.org/category/5/xkavc-ip-core

    • ]]>    http://www.openasic.org/topic/160/xkavc-encoder-k3-pe-evaluation-edition-releasedhttp://www.openasic.org/topic/160/xkavc-encoder-k3-pe-evaluation-edition-releasedWed, 21 Jun 2023 04:22:23 GMT    <![CDATA[xkAVC Encoder (K3.ie) Evaluation Edition Released]]>xkAVC Baseline Encoder（K3）

    • Feature List
      Supported Platform : ZCU102 (xczu9eg-ffvb1156-2-e)
      Performance : ~1920x1080 @ 60fps @ 120MHz
      Profile: AVC Baseline
      Supported Frame Type: I P Frame
      Picture Format: YUV420
      Pixel Depth: 8-bit
      LCU Size: 16x16
      QP Range: 0-51

    • K3.ie Implementation Results (FPGA)
      Platform: ZCU102 FPGA Board
      Frequency: 120MHz
      LUT: (274080) 52414
      BRAM: (912) 9.5
      DSP: (2520) 112
      LUTRAM: (144000) 4138
      FF: (548160) 30919

    • Download
      http://xk.openasic.org/product/3

    • Q&A
      Any question can be submit here : http://openasic.org/category/5/xkavc-ip-core

    ]]>    http://www.openasic.org/topic/156/xkavc-encoder-k3-ie-evaluation-edition-releasedhttp://www.openasic.org/topic/156/xkavc-encoder-k3-ie-evaluation-edition-releasedThu, 01 Jun 2023 01:42:50 GMT    <![CDATA[H264 ENCODER RTL V2.0仿真及FPGA教程_v2]]>http://www.openasic.org/topic/119/h264-encoder-rtl-v2-0仿真及fpga教程_v2http://www.openasic.org/topic/119/h264-encoder-rtl-v2-0仿真及fpga教程_v2Thu, 19 Aug 2021 04:59:17 GMT<![CDATA[IP SoC China 2020 演讲Video]]>IP SoC China 2020
    网址：https://www.design-reuse-embedded.com/ipsocdays/ipsocdays2020/china2020/welcome.jsp

    视频地址：
    https://www.design-reuse-embedded.com/ipsocdays/ipsocdays2020/china2020/video.jsp?k=Yibo%2BFan

    优酷地址：
    https://v.youku.com/v_show/id_XNDg0NzA1MzE1Mg==.html?spm=a1z3jc.11711052.0.0&isextonly=1

    ]]>    http://www.openasic.org/topic/103/ip-soc-china-2020-演讲videohttp://www.openasic.org/topic/103/ip-soc-china-2020-演讲videoTue, 15 Sep 2020 08:03:34 GMT    <![CDATA[H264 ENCODER RTL V2.0仿真教程]]>http://www.openasic.org/topic/82/h264-encoder-rtl-v2-0仿真教程http://www.openasic.org/topic/82/h264-encoder-rtl-v2-0仿真教程Fri, 02 Aug 2019 11:30:02 GMT<![CDATA[H.264/AVC Encoder IP Core V2.0 综合结果]]>

  • DC with TSMC65nm under 400MHz
    0_1564744893151_TSMC65nm.png

  • Xilinx FPGA
    0_1564745135478_FPGA.png

    • ]]>    http://www.openasic.org/topic/81/h-264-avc-encoder-ip-core-v2-0-综合结果http://www.openasic.org/topic/81/h-264-avc-encoder-ip-core-v2-0-综合结果Fri, 02 Aug 2019 11:25:24 GMT    <![CDATA[开源H.264 Video Encoder IP Core V2.0 发布]]>http://www.openasic.org/topic/80/开源h-264-video-encoder-ip-core-v2-0-发布http://www.openasic.org/topic/80/开源h-264-video-encoder-ip-core-v2-0-发布Thu, 01 Aug 2019 01:54:40 GMT<![CDATA[开源H.265/HEVC Encoder IP Core V2.0发布]]>http://www.openasic.org/topic/73/开源h-265-hevc-encoder-ip-core-v2-0发布http://www.openasic.org/topic/73/开源h-265-hevc-encoder-ip-core-v2-0发布Thu, 20 Jun 2019 00:48:11 GMT<![CDATA[H265 ENCODER RTL V2.0仿真教程]]>http://www.openasic.org/topic/72/h265-encoder-rtl-v2-0仿真教程http://www.openasic.org/topic/72/h265-encoder-rtl-v2-0仿真教程Tue, 18 Jun 2019 04:11:12 GMT<![CDATA[基于PYNQ的H.264演示Demo]]>http://www.openasic.org/topic/61/基于pynq的h-264演示demohttp://www.openasic.org/topic/61/基于pynq的h-264演示demoFri, 15 Jun 2018 02:15:52 GMT<![CDATA[开源H.264 Video Decoder IP Core发布]]>

    Brief

    Model Osen Logic OSD10 h.264 decoder
    Profile Baseline
    Level 3.1
    Input Format H.264 NAL stream
    Output Format YUV4:2:0
    Bitdepth 8
    Slice type supported I,SI,P,SP
    Entropy Coding CAVLC
    Supported frme size Max: 1920x1088,Min:640x480
    Supported bitrate 0 to 10Mps,No decode rate control
    Max resolution and frame rate 1920x1088 @ 30fps, working at 75M
    Required external memory size 32Mbyte
    Memory interface data width 64bit

    Download

    http://openasic.org/topic/48/h-264-decoder-ip-core-rtl-code-v1-0

    Thanks

    Many Thanks to @eebq for sharing his code to OpenASIC

    关注我们

    微信公众号： OpenASIC
    img

    ]]>    http://www.openasic.org/topic/50/开源h-264-video-decoder-ip-core发布http://www.openasic.org/topic/50/开源h-264-video-decoder-ip-core发布Mon, 12 Jun 2017 10:03:02 GMT    <![CDATA[Bs2Hevc代码发布]]>A tiny software to translate bit-stream from RTL (ASCII text) to hevc bit-stream (binary)

    input ASCII text format

    /test/bs_g5_416x240_f10.dat (exmaple)
    @0 -- frame number 0, added manually
    XX -- bit stream byte generated by RTL testbench
    XX
    XX
    ....
    @1
    XX
    XX
    XX
    ....

    output bitstream

    /test/bs.hevc

    run

    /test/vs2010.exe

    download

    http://openasic.org/topic/45/bs2hevc

    关注我们

    微信公众号：OpenASIC
    img

    ]]>    http://www.openasic.org/topic/46/bs2hevc代码发布http://www.openasic.org/topic/46/bs2hevc代码发布Mon, 22 May 2017 06:34:40 GMT    <![CDATA[开源H.264 Video Encoder IP Core发布]]>http://www.openasic.org/topic/43/开源h-264-video-encoder-ip-core发布http://www.openasic.org/topic/43/开源h-264-video-encoder-ip-core发布Fri, 12 May 2017 09:05:16 GMT<![CDATA[2017.1.13 IC Caffe线下研讨会PPT文档]]>http://www.openasic.org/topic/32/2017-1-13-ic-caffe线下研讨会ppt文档http://www.openasic.org/topic/32/2017-1-13-ic-caffe线下研讨会ppt文档Sat, 14 Jan 2017 08:23:26 GMT<![CDATA[H.265 Video Encoder FPGA Demo Video]]>http://www.openasic.org/topic/23/h-265-video-encoder-fpga-demo-videohttp://www.openasic.org/topic/23/h-265-video-encoder-fpga-demo-videoTue, 27 Dec 2016 11:40:09 GMT<![CDATA[关于这个开源项目 from VIP Lab]]>http://www.openasic.org/topic/14/关于这个开源项目-from-vip-labhttp://www.openasic.org/topic/14/关于这个开源项目-from-vip-labFri, 23 Dec 2016 07:27:32 GMT<![CDATA[H.265 Encoder FPGA Demo System 演示系统架构]]>http://www.openasic.org/topic/11/h-265-encoder-fpga-demo-system-演示系统架构http://www.openasic.org/topic/11/h-265-encoder-fpga-demo-system-演示系统架构Thu, 22 Dec 2016 08:52:07 GMT<![CDATA[H.265/HEVC Encoder IP Architecture 系统架构]]>http://www.openasic.org/topic/9/h-265-hevc-encoder-ip-architecture-系统架构http://www.openasic.org/topic/9/h-265-hevc-encoder-ip-architecture-系统架构Thu, 22 Dec 2016 08:06:28 GMT<![CDATA[VIP Lab (Video Image Processing Lab) @ Fudan University]]>

    VIP 实验室

    复旦大学VIP实验室由范益波教授（Prof. Yibo Fan）创建，实验室专注于从事下一代视频、图像硬件处器研究，包括超高清视频编码器（H.264/H.265 Video Encoder IP），图像去雾（Dehazing）处理器，双目视觉处理器（Stereo Matching）等。

    关注我们

    微信公众号： OpenASIC
    img

    ]]>    http://www.openasic.org/topic/8/vip-lab-video-image-processing-lab-fudan-universityhttp://www.openasic.org/topic/8/vip-lab-video-image-processing-lab-fudan-universityThu, 22 Dec 2016 08:04:16 GMT    <![CDATA[H.265 Video Encoder IP RTL Simulation 方法]]>http://www.openasic.org/topic/7/h-265-video-encoder-ip-rtl-simulation-方法http://www.openasic.org/topic/7/h-265-video-encoder-ip-rtl-simulation-方法Thu, 22 Dec 2016 07:27:02 GMT<![CDATA[首款开源H.265 Video Encoder IP Core发布]]>http://www.openasic.org/topic/5/首款开源h-265-video-encoder-ip-core发布http://www.openasic.org/topic/5/首款开源h-265-video-encoder-ip-core发布Thu, 22 Dec 2016 07:05:31 GMT